1. Field of the Invention
The embodiments herein relate to processors and, more particularly, to implementation of data prefetch systems.
2. Description of the Related Art
To improve execution performance, a processor may include one or more levels of cache memories (commonly referred to as “caches”). A cache may be used to store frequently accessed instructions and/or memory data, and improve performance by reducing the time for the processor to retrieve these instructions and data. A processor may include a fast low/first-level (L1) cache backed by a larger, slower second-level (L2) cache. Some processors may include a high/third-level (L3) cache for further performance improvement. Processors may include multiple cores and/or cores that execute multiple software processes at a same time.
Some processors may include a prefetch buffer for a given cache to further improve memory access times. A prefetch buffer for the given cache may read data from a higher level cache or a system memory in anticipation of an upcoming request from the cache, i.e., prefetch data before the processor requests the data. A prefetch buffer may learn memory access patterns corresponding to one of more software processes running in the processor. Using these patterns, the prefetch buffer may then read data before the cache request it.
In cases in which a prefetch buffer supports more than one core or a core executing multiple software processes, the prefetch buffer may experience interference between the multiple software processes while learning memory access patterns. Memory access patterns may be overlapping, causing the prefetch buffer to recognize an incorrect pattern. In some cases, this may lead to less optimal memory prefetches and possibly increased cache misses.